superscalar - definizione. Che cos'è superscalar
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Cosa (chi) è superscalar - definizione

CPU THAT IMPLEMENTS INSTRUCTION-LEVEL PARALLELISM WITHIN A SINGLE PROCESSOR
Superscalar architecture; Superscaler; Super-scalar architecture; Superscalar; Superscalar execution
  • CRAY T3e]] supercomputer with four ''superscalar'' [[Alpha 21164]] processors
  • Simple superscalar pipeline. By fetching and dispatching two instructions at a time, a maximum of two instructions per cycle can be completed. (IF = instruction fetch, ID = instruction decode, EX = execute, MEM = memory access, WB = register write-back, ''i'' = instruction number, ''t'' = clock cycle [i.e. time])

superscalar         
<architecture> A superscalar architecture is a uniprocessor that can execute two or more scalar operations in parallel. Some definitions include superpipelined and VLIW architectures; others do not. Superscalar architectures (apart from superpipelined architectures) require multiple functional units, which may or may not be identical to each other. In some superscalar processors the order of instruction execution is determined statically (purely at compile-time), in others it is determined dynamically (partly at run time).
VLIW         
INSTRUCTION SET ARCHITECTURE
Static superscalar; VLIW; Very Long Instruction Word; Vliw; MPPA MANYCORE; Variable length instruction word
VLIW         
INSTRUCTION SET ARCHITECTURE
Static superscalar; VLIW; Very Long Instruction Word; Vliw; MPPA MANYCORE; Variable length instruction word
Very Long Instruction Word (Reference: CPU, IC)

Wikipedia

Superscalar processor

A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor, which can execute at most one single instruction per clock cycle, a superscalar processor can execute more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to different execution units on the processor. It therefore allows more throughput (the number of instructions that can be executed in a unit of time) than would otherwise be possible at a given clock rate. Each execution unit is not a separate processor (or a core if the processor is a multi-core processor), but an execution resource within a single CPU such as an arithmetic logic unit.

In Flynn's taxonomy, a single-core superscalar processor is classified as an SISD processor (single instruction stream, single data stream), though a single-core superscalar processor that supports short vector operations could be classified as SIMD (single instruction stream, multiple data streams). A multi-core superscalar processor is classified as an MIMD processor (multiple instruction streams, multiple data streams).

While a superscalar CPU is typically also pipelined, superscalar and pipelining execution are considered different performance enhancement techniques. The former executes multiple instructions in parallel by using multiple execution units, whereas the latter executes multiple instructions in the same execution unit in parallel by dividing the execution unit into different phases.

The superscalar technique is traditionally associated with several identifying characteristics (within a given CPU):

  • Instructions are issued from a sequential instruction stream
  • The CPU dynamically checks for data dependencies between instructions at run time (versus software checking at compile time)
  • The CPU can execute multiple instructions per clock cycle